1. Field of the Invention
This invention is related to electrostatic discharge (ESD) protection circuits for integrated circuits formed on a semiconductor substrate. More particularly, this invention relates to ESD protection circuits that have gate driven charge dissipation transistors.
2. Description of the Related Art
Electrostatic discharge (ESD) damage has become one of the main reliability concerns on the integrated circuit (IC) products. Especially, now that complementary metal oxide semiconductor (CMOS) technology has been developed into the deep-submicron lithographic feature size, the scaled-down metal oxide semiconductor (MOS) devices and thinner gate oxide has become more vulnerable to the extreme voltage level from contact with an ESD source. For general industrial specification, the input and output pins of the IC products have to sustain the extreme voltage level from contact with an ESD source of above 2000V. Therefore, the ESD protection circuits have to be placed around the input and output pads of the IC's to protect the IC's against the ESD damage, by shunting the electrostatic charges present at the ESD source from the IC's.
A typical input ESD protection circuit is shown in FIG. 1. The input pad 5 is connected to the internal integrated circuits 15 and the ESD protection device 10. When an ESD source is brought in contact with the input pad 5 the ESD protection device 10 is forced into an avalanche breakdown causing the ESD protection device to conduct dramatically, thus dissipating the electrostatic charge from the ESD source.
The ESD protection device 10 is a gate grounded n-type MOS (GGnMOS) transistor Mn110 having its source, bulk, and gate connected to the substrate biasing voltage source VSS. The substrate biasing voltage source VSS may be an independent negative voltage source or the ground reference point. The drain of the GGnMOS transistor Mn110 is connected to input pad 5.
In order to sustain a high ESD current, the gate-grounded NMOS (often called GGnMOS) Mn110 in FIG. 1 is drawn with relatively a large device dimension, such as W/L=500 .mu.m/0.5 .mu.m in a typical 0.35 .mu.m CMOS technology. With such a large device dimension, the GGnMOS transistor Mn110 is typically drawn with multiple fingered of polycrystalline silicon gates. The typical layout example of the GGnMOS transistor Mn110 for ESD protection as shown in FIG. 2 had been described in "Methodology For Layout Design And Optimization Of ESD Protection Transistors," S. G. Beebe, 1996 EOS/ESD Symp. Proc., pp.265-275.
The GGnMOS transistor Mn110 is connected to the input pad 5 with the metal lands 20. The metal lands 20 are connected to the N+ drain diffusion 25 of the GGnMOS transistor Mn110. The N+ source diffusions 30 are connected together and to the substrate biasing voltage source VSS. Multiple fingers 35 of heavily doped polycrystalline silicon form the gates of the GGnMOS transistor Mn110. The gates 35 of the GGnMOS transistor Mn110 are connected through the metal land 40 to the substrate biasing voltage source VSS.
It has been found that the GGnMOS transistor Mn110 having a relatively large device dimension can sustain only a relatively low ESD voltage level, because the multiple heavily doped polycrystalline silicon gates 35 cannot uniformly turn on the GGnMOS transistor Mn110 during the extreme voltage level from contact with an ESD source as described in "Improving The ESD Failure Threshold Of Silicided NMOS Output Transistors By Ensuring Uniform Current Flow," T. L. Polgreen et al., IEEE Trans. Electron Devices, vol. 39, pp. 379-388, 1992.
Since only some regions of the GGnMOS transistor Mn110 are turned on, the charge to be conducted from the ESD source causes the current density within the channel of those turned-on regions to be large. This causes damage to several of the fingers of the gates of the GGnMOS transistor Mn110. So, even though the GGnMOS transistor Mn110 has a relatively large device dimension, it is effectively a much smaller transistor that cannot sustain the large ESD current.
In order to improve the tolerance of the ESD protection device to the extreme voltage levels from the ESD source, the multiple heavily doped polycrystalline silicon gates 35 of the ESD protection NMOS transistor Mn110 have to be uniformly turned on to share the current from the ESD source. If all the heavily doped polycrystalline silicon gates 35 of the ESD protection NMOS transistor Mn110 can be uniformly turned on during the extreme voltage level from contact with an ESD source, the ESD protection NMOS transistor Mn110 can sustain high levels of voltage from the ESD source as described by T. L. Polgreen et al.
To achieve the uniform turn-on behavior among the multiple heavily doped polycrystalline silicon gates 35 of the MOS transistor Mn1, a gate-driven technique is described in U.S. Pat. No. 4,855,620 (C. Duvvury et al.); U.S. Pat. No. 5,086,365 (C. -D. Lien); "Dynamic Gate Coupling Of NMOS For Efficient Output ESD Protection," C. Duvvury et al., Proc. of IRPS, 1992, pp. 141-150; "Achieving Uniform NMOS Device Power Distribution For Submicron ESD Reliability," C. Duvvury et al., Tech. Dig IEDM, 1992, pp. 131-134; "EOS/ESD Reliability Of Deep Sub-Micron NMOS Protection Devices," S. Ramaswamy et al., Proc. of IRPS, 1995, pp. 284-291; "Capacitor-Couple ESD Protection Circuit For Deep-Submicron Low-Voltage CMOS ASIC," M. -D. Ker et al., IEEE Trans. on VLSI Systems, vol. 4, pp. 307-321, September, 1996; and U.S. Pat. No. 5,631,793 (M. -D. Ker et al.).
This improves the tolerance of the MOS transistor Mn1 to the extreme voltage levels from contact with the ESD source. The structure of a gate-driven input ESD protection circuit is shown in FIG. 3. An ESD-detection circuit is connected from the input pad 5 to the gate of the ESD protection NMOS transistor Mn110. When the pad 5 is exposed to the extreme voltage level of an ESD source, the ESD-detection circuit 45 will generate a voltage VG to bias the gate of the ESD protection NMOS transistor Mn110. Therefore, the voltage level at the multiple heavily doped polycrystalline silicon gates 35 of the ESD protection NMOS transistor Mn110 causes the ESD protection NMOS transistor Mn110 to be uniformly turned on to dissipate the charge from the ESD source and allow the integrated circuit to withstand a higher voltage level present at the ESD source. A typical gate-driven design for an input ESD protection circuit is shown in FIG. 4, where the ESD-detection circuit can be simply realized by a capacitor C 50 and a resistor R 55. The capacitor C 55 is connected from the input pad 5 to the gate of the ESD protection NMOS transistor Mn110 and the gate of the ESD protection NMOS transistor Mn110 is connected to the substrate biasing voltage source VSS through a resistor R 55. The capacitor C 40 is used to couple the ESD transient voltage level of the ESD voltage source from the pad 5 to the gate of the ESD protection NMOS transistor Mn110. With a coupled voltage VG on the gate of the ESD protection NMOS transistor Mn110, all the heavily doped polycrystalline silicon gates 35 of the ESD protection NMOS transistor Mn110 can be uniformly turned on to bypass the ESD current and dissipate the charge from the ESD source.
Therefore, the voltage level of the ESD source that the ESD protection NMOS transistor Mn110 can sustain before failure can be effectively improved. To maintain the coupled voltage VG on the gate of the ESD protection NMOS transistor Mn110, a resistor Rn 55 is added from the gate of the ESD protection NMOS transistor Mn110 to the substrate biasing voltage source VSS. When the ESD-transient voltage from the ESD voltage source connected to the input pad 5 is coupled through the capacitor C 50 to the gate of the ESD protection NMOS transistor Mn110, such coupled voltage VG is held longer in time as a result of the time constant of the resistor R 55 and the capacitor C 50. So, the ESD protection NMOS transistor Mn110 can be efficiently turned on to bypass the ESD current and dissipate the electrostatic charge from the ESD source. Such a gate-coupled NMOS (GCnMOS) transistor is described in "Dynamic Gate Coupling Of NMOS For Efficient Output ESD Protection," C. Duvvury et al., Proc. of IRPS, 1992, pp. 141-150; "Achieving Uniform NMOS Device Power Distribution For Submicron ESD Reliability," C. Duvvury et al., in Tech. Dig IEDM, 1992, pp. 131-134; "EOS/ESD Reliability Of Deep Sub-Micron NMOS Protection Devices," S Ramaswamy et al., in Proc. of IRPS, 1995, pp. 284-291.
An alternative embodiment of the gate-driven ESD protection circuit as shown in FIG. 5 is described in "Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC," M. -D. Ker et al., IEEE Trans. on VLSI Systems, vol.4, pp. 307-321, September, 1996; U.S. Pat. No. 5,631,793 (M. -D. Ker et al.). In this alternate embodiment the gate-driven technique is applied to both the ESD protection NMOS transistor Mn110 and the PMOS transistor Mp160 in the input ESD protection circuit to achieve the uniform turn-on and therefore uniform current density in the ESD protection NMOS transistor Mn110 and the PMOS transistor Mp160.
The first ESD protection NMOS transistor Mn110 and the first charge detection circuit 45 are structured and perform as described in FIG. 4. The second charge detection circuit 65 is constructed of the capacitor Cp 70 and the resistor Rp 75. The capacitor Cp 70 is connected between the input pad 5 and the gate of the ESD protection PMOS transistor Mp160. The resistor Rp 75 is connected between the gate of the ESD protection PMOS transistor Mp160 and the power supply voltage source VDD. The drain of the ESD protection PMOS transistor Mp160 is connected to the power supply voltage source VDD. The source of the ESD protection PMOS transistor Mp160 is connected to the input pad 5.
To further protect the internal circuits of an IC, an ESD protection circuit must be placed between the power supply voltage source VDD and the substrate biasing voltage source VSS power distribution terminals of the IC as discussed in "Whole-Chip ESD Protection Design With Efficient VDD-To-VSS ESD Clamp Circuit For Submicron CMOS VLSI," M. -D. Ker, IEEE Trans. on Electron Devices, vol. 46, no. 1, pp. 173-178, January, 1999 (M. -D. Ker ED 46).
Some effective ESD protection circuits for placing between the power supply voltage source VDD and substrate biasing voltage source VSS power distribution terminals have been described in M. -D. Ker ED 46; "ESD Design Methodology," R. Merrill et al., EOS/ESD Symp. Proc., 1993, EOS-15, pp. 233-237; "Core Clamps For Low Voltage Technologies," S. Dabral et al., EOS/ESD Symp. Proc., 1994, EOS-16, pp. 141-149; "Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions," B. R. Worley et al., EOS/ESD Symp. Proc., 1995, EOS-17, pp. 13-20; U.S. Pat. No. 5,237,395 (K. F. Lee); U.S. Pat. No. 5,255,146 (W. Miller); U.S. Pat. No. 5,287,241 (D. S. Puar); U.S. Pat. No. 5,311,391 (T. Dungan et al.); U.S. Pat. No. 5,440,162 (B. R. Worley et al.); U.S. Pat. No. 5,610,791 (S. Voldman); and U.S. Pat. No. 5,625,280 (S. Voldman).
In such power supply voltage source to substrate biasing voltage source VDD-to-VSS ESD protection circuits, the gate-driven technique is also applied to turn on the ESD protection NMOS transistor. Another embodiment of a power supply voltage source to substrate biasing voltage source VDD-to-VSS ESD protection circuit using the gate-driven technique is illustrated in FIG. 6.
In this embodiment, the ESD protection NMOS transistor Mn110 has its drain connected to the power supply voltage source VDD and its source connected to the substrate biasing voltage source VSS. The ESD detection circuit 45 has its input ports connected to the power supply voltage source VDD and the substrate biasing voltage source VSS. The ESD detection circuit 45 is formed of the resistor R 85, the capacitor C 80, the NMOS buffer transistor Mn290, and the PMOS buffer transistor Mp295. The resistor R 80 is connected between the input port connected to the power supply voltage source VDD and the common connection of the gates of the NMOS buffer transistor Mn290, and the PMOS buffer transistor Mp295. The capacitor C 80 in this embodiment is formed of an NMOS transistor having its gate connected to the commonly connected gates of the NMOS buffer transistor Mn290, and the PMOS buffer transistor Mp295. The drain, source, and bulk of the NMOS transistor that forms the capacitor C 80 are commonly connected to the input port of the ESD detection circuit connected to the substrate biasing voltage source VSS.
In this embodiment of the ESD-detection circuit, the resistor R 80 and the capacitor C 85 have an RC time constant from approximately 0.1 .mu.sec to approximately 1.0 .mu.sec to detect the ESD transition across the power supply voltage source VDD and substrate biasing voltage source VSS. The ESD protection NMOS transistor Mn110 can be quickly turned on to clamp the ESD overstress voltage across the power supply voltage source VDD and substrate biasing voltage source VSS lines. This embodiment is a typical application of gate-driven technique in the ESD protection circuit. But, when the CMOS transistor dimensions enter into the deep-submicron lithographic feature size, the shallower junction depth, the LDD (lightly-doped drain) structure, and the silicided diffusion cause a lower ESD level to be sustained by the ESD protection NMOS transistor Mn110. These effects are explained in "Scaling, Optimization And Design Consideration Of Electrostatic Discharge Protection Circuits In CMOS Technology," S. Voldman et al., EOS/ESD Symp. Proc., pp. 251-260, 1993; "The Impact Of Technology Scaling On ESD Robustness And Protection Circuit Design," A. Amerasekera et al., EOS/ESD Symp. Proc., pp. 237-245, 1994; and "Process And Design Optimization For Advanced CMOS I/O ESD Protection Devices," S. Daniel et al., EOS/ESD Symp. Proc., pp. 206-213, 1990.
The ESD protection NMOS transistor Mn110 between the power supply voltage source VDD and substrate biasing voltage source VSS terminals are therefore designed with a huge device dimension to sustain a desired ESD voltage level. This transistor then consumes a large silicon area on a silicon substrate when the IC's are formed.
It is shown that the gate voltage VG on the ESD protection NMOS transistor Mn110 can be sufficiently large to cause damage at a much lower ESD voltage level than its original ESD voltage level without gate bias. This phenomenon is discussed in "Substrate Triggering And Salicide Effects On ESD Performance And Protection Circuit Design In Deep Submicron CMOS Process," A. Amerasekera, et al., IEDM Tech. Dig., 1995, pp. 547-550; "Design Methodology For Optimized Gate Driven ESD Protection Circuits In Submicron CMOS Processes," J. Chen, et al., Proc. of EOS/ESD Symp., pp. 230-239, 1997; "Design Methodology And Optimization Of Gate-Driven NMOS ESD Protection Circuits In Submicron CMOS Processes," J. Chen, et al., IEEE Trans, on Electron Devices, vol. 45, no. 12, pp. 2448-2456, December, 1998; and "ESD Protection For Mixed-Voltage I/O Using NMOS Transistors Stacked In A Cascade Configuration," W. Anderson et al., Proc. of EOS/ESD Symp., pp. 54-62, 1998, and is illustrated in FIG. 7.
The ESD protection NMOS transistor Mn110 is formed in the semiconductor substrate 100. The drain 105 of the ESD protection NMOS transistor Mn110 is created by diffusing an N+ material into the surface of the semiconductor substrate 100. Likewise, the source 115 is created by diffusing the N+material into the surface of the semiconductor substrate 100. A lightly doped N material is diffused into the surface of the semiconductor substrate 100 to form the lightly doped drain areas 125 and 130 respectively adjacent to the drain 105 and the source 115. In the region between drain 105 and the source 115, and insulating material is formed to form the gate oxide 120. On the gate oxide, a conductive material such as heavily doped polycrystalline silicon is formed to create the gate 110. A heavily doped P-type material is diffused into the surface of the semiconductor substrate 100 to form the contact point 140 to the semiconductor substrate 100. A metal such as Titanium (Ti) or Tungsten (W) are alloyed with the silicon of the semiconductor substrate to form the silicide areas 145 and 150. The suicide areas 145 and 150 insure a low resistivity contact from the drain 105, the source 115 and the substrate contact 140 to external circuitry.
The pad 5 is connected to the drain 105 and one of the input ports of the ESD detection circuit 45. The source 115 and the substrate contact 140 are connected through the metal land 155 to the substrate biasing voltage source VSS. As described above, the second input port of the ESD detection circuit 45 is connected to the substrate biasing voltage source VSS. The output port of the ESD detection circuit 45 is connected to the gate 110.
While the ESD source 160 is connected to the PAD 5, the ESD-detection circuit 45 will detect the ESD voltage level VESD and generate a voltage VG to bias the gate of the ESD protection NMOS transistor Mn110. Therefore, the ESD protection NMOS transistor Mn110 is quickly turned on to bypass the overstress ESD current IESD. However, in the deep-submicron CMOS process, if the voltage level VG at the gate 110 of the ESD protection NMOS transistor Mn110 is at a high voltage level during the extreme voltage level from contact with an ESD source, a surface channel 135 of the ESD protection NMOS transistor Mn110 is formed, and the ESD current IESD is discharged through the much shallower surface channel 135 of the ESD protection NMOS transistor Mn110. The ESD current IESD is often on the order of several amperes (A). For example, a 2 -KV human-body-model (HBM) ESD event can generate an ESD current IESD of about 1.33 A. Such a large ESD current flowing through the shallower surface channel 135 forces a very high current density and can easily destroy the ESD protection NMOS transistor Mn110 even if the ESD protection NMOS transistor Mn110 has a relatively huge device dimension. Thus, this phenomenon generally causes a much lower voltage level to be sustained by the ESD protection NMOS transistor Mn110. This phenomenon has been referred to as the "overstress gate-driven effect".
To practically demonstrate the gate-driven effect on the ESD protection NMOS transistor Mn110 and ESD protection PMOS transistor Mp160 in the deep-submicron CMOS process, an experimental measurement setup is shown in FIGS. 8a and 8b. In FIG. 8a, a ESD protection NMOS transistor Mn110 is fabricated by using a 0.35 .mu.m, CMOS process.
A gate biasing voltage source 170 is connected between the gate of the ESD protection NMOS transistor Mn110 and the substrate biasing voltage source VSS. The substrate biasing voltage source VSS is then connected to the ground reference point. The drain of the ESD protection NMOS transistor Mn110 is connected to the pad 5. A test ESD voltage source 160 is connected between the pad 5 and the ground reference point and provides an ESD voltage V.sub.ESD having a positive polarity.
In FIG. 8b, the gate biasing voltage source is connected between the gate of the ESD protection PMOS transistor Mp160 and the power supply voltage source VDD. For this test structure, the terminal of the integrated circuit that is normally connected to the power supply voltage source VDD is now connected to the ground reference point. The source of the ESD protection PMOS transistor Mp160 is connected to the terminal of the integrated circuit normally connected to the power supply voltage source VDD. The drain of the ESD protection PMOS transistor Mp160 is connected to the pad 5. The test ESD voltage source 160 is again connected between the input pad 5 and the ground reference point. The test ESD voltage source 160, in this test, provides an ESD voltage with a negative polarity.
The ESD-sustained level of the test of the gate-driven ESD protection NMOS transistor Mn110 is summarized and shown in FIG. 9. The ESD protection NMOS transistor Mn110 in the ESD test have a channel length of 0.8 .mu.m. The ESD protection NMOS transistor Mn110 with a channel width of 600 .mu.m has a human-body-model (HBM) ESD voltage level sustainable of only about 2.2 kV while the voltage level of the gate biasing voltage source VG 170 is 0V 175. But, the HBM ESD voltage level sustainable by the ESD protection NMOS transistor Mn110 can be increased to 4 kV when the voltage level of the gate biasing voltage source VG 170 is increased to 3V. The improvement on the ESD voltage level sustainable by the ESD protection NMOS transistor Mn110 with a positive voltage level of gate biasing voltage source VG 170 is due to the uniform turn-on along the multiple heavily doped polycrystalline silicon gates 35 of the ESD protection NMOS transistor Mn110 during the application of the extreme voltage level from contact with an ESD source. But, when the voltage level of the gate biasing voltage source VG 170 is greater than 9V, the ESD voltage level sustainable by the ESD protection NMOS transistor Mn110 is sharply dropped to a much lower level of around 100V 185. When the ESD protection NMOS transistor Mn110 has a device channel width of 200 .mu.m, its ESD voltage level is increased as the voltage level of the gate biasing voltage source VG 170 is increased 190. But, when the voltage level of the gate biasing voltage source VG 170 is greater than 6V, its ESD voltage level sustainable by the ESD protection NMOS transistor Mn110 with 200 .mu.m channel width is dropped down to a much lower voltage level 195. From the experimental results in FIG. 9, it is shown that a ESD protection NMOS transistor Mn110 with an over-biased gate voltage causes a much lower ESD voltage level than its original ESD voltage level without the voltage level of the gate biasing voltage source VG 170 voltage. This overstress gate-driven effect causes a much lower ESD voltage level sustainable by the ESD protection NMOS transistor Mn110 in deep-submicron CMOS process as reported in "Substrate Triggering And Salicide Effects On ESD Performance And Protection Circuit Design In Deep Submicron CMOS Process," A. Amerasekera, et al., IEDM Tech. Dig., 1995, pp. 547-550; "Design Methodology For Optimized Gate Driven ESD Protection Circuits In Submicron CMOS Processes," J. Chen, et al., Proc. of EOS/ESD Symp., pp. 230-239, 1997; "Design Methodology And Optimization Of Gate-Driven NMOS ESD Protection Circuits In Submicron CMOS Processes," J. Chen, et al., IEEE Trans, on Electron Devices, vol. 45, no. 12, pp. 2448-2456, December, 1998; and "ESD Protection For Mixed-Voltage I/O Using NMOS Transistors Stacked In A Cascade Configuration," W. Anderson et al., Proc. of EOS/ESD Symp., pp. 54-62,1998.
The results of the experiments to demonstrate the gate-driven effect on the ESD protection PMOS transistor Mp160 as described in FIG. 8b are summarized in FIG. 10. In FIG. 10, the negative HBM ESD voltage level sustainable by the ESD protection PMOS transistor Mp160 in a 0.35 .mu.m CMOS process is slightly increased when the negative voltage level of the gate biasing voltage source VG 170 is increased. But, when the negative voltage level of the gate biasing voltage source VG 170 is lower than -5V, its ESD voltage level sustainable by the ESD protection PMOS transistor Mp160 sharply decreases to a much lower level 200. This experimental result verifies that the overstress gate-driven effect also has a negative impact on the ESD voltage level sustainable by the ESD protection PMOS transistor Mp160 in the deep-submicron CMOS process.
In summary, the gate-driven technique, which was previously reported to improve the ESD voltage level sustainable by the ESD protection MOS transistor can cause the unexpected serious degradation on the ESD voltage level sustainable by the ESD protection MOS transistor if its gate is over-biased with an extremely high voltage. However, as shown in the prior art, the ESD protection circuits having the gate-driven technique do not limit the gate voltage level of the charged dissipating MOS transistor.